1. Field of the Invention
The present invention relates to microprocessors and more particularly to a method and means for eliminating unwanted latency in the execution of interrupt signals which produce regular time period interrupts that allow tasks to be dispatched on a real-time periodic basis.
2. Problem to be Solved
In modern microprocessor systems, it is often necessary to provide the appearance of a real-time processor for certain system functions. An example is found in digital signal processor applications where there is a need for an interrupt mechanism for real time preemptive multi-tasking since it is required that tasks be dispatched on a real-time periodic basis. This is difficult to achieve due to the existence of certain functions that the microprocessor must perform that have unpredictable interrupt latency.
In conventional microprocessor implementations, instructions are executed through a module of code performing architected events. Each individual instruction may require several machine or other clock cycles to complete and the number of cycles required by each instruction may vary due to complexity, amount of data handled, resource required, Virtual to Real address translation, Cache hit or miss, and such. In modern microprocessors, performance is improved by using various methods that reduce the apparent number of cycles needed to execute the instructions, e.g., pipe-lining, branch guessing, out-of-order execution, multiple fetch and execution, etc. Further, outside influences, such as memory utilization, I/O utilization, exception handling, and the like, may cause a particular instruction to perform differently at different times.
From the foregoing, it will be appreciated that complex events effect the performance of an individual instruction as well as that of a module (group) of instructions. A problem is presented by this performance variation in certain applications where it is required to provide interrupt capability at precise intervals. With all the events effecting the performance of a microprocessor instruction stream it is clear that some events may severely impact the interrupt latency, for instance, when an instruction has an outstanding memory request that it cannot complete until the memory operation has completed. If the memory is not available, e.g., when another microprocessor has the current Line in a multi-processor environment, the instruction could be delayed in completion for a considerable time.
The functions that may add latency to an interrupt request being serviced vary by implementation and by type. It is therefore desirable that a system or mechanism be provided that eliminates the effect of various machine functions on latency and that preferably is programmable so that a system implementer can adjust for his particular requirements.